Recent technological advances in the semiconductor industry have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Presently, single-die microprocessors are being manufactured with many millions of transistors, operating at speeds of hundreds of millions of instructions per second and being packaged in relatively small, air-cooled semiconductor device packages. The improvements in such devices have led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has also increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important.
An important part in the design, construction, and manufacture of semiconductor devices concerns semiconductor memory and other current-switching circuitry. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (e.g., high density has benefits including low price), with DRAM cell size being typically between 6 F2 and 8 F2, where F is the minimum feature size. However, with typical DRAM access times of approximately 50 nSec, DRAM is relatively slow compared to typical microprocessor speeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is of an order of magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically constructed using 4 transistors and 2 resistors or 6 transistors, which result in much lower density and is typically between about 60 F2 and 100 F2.
Various SRAM cell designs based on a NDR (Negative Differential Resistance) construction have been introduced, ranging from a simple bipolar transistor to complicated quantum-effect devices. These cell designs usually consist of at least two active elements, including an NDR device. In view of size considerations, the construction of the NDR device is important to the overall performance of this type of SRAM cell. One advantage of the NDR-based cell is the potential of having a cell area smaller than four-transistor and six-transistor SRAM cells because of the smaller number of active devices and interconnections.
Concerns with NDR-type circuits and memory include, among others: high standby power consumption due to the large current needed in one or both of the stable states of the cell; requiring excessively high or excessively low voltage levels for cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
A thin capacitively-coupled thyristor-type NDR device can be effective in overcoming many previously unresolved problems for a variety of semiconductor applications, such as memory applications. An important consideration in the design of a thin capacitively-coupled thyristor involves designing the body of the thyristor sufficiently thin, such that capacitive coupling between a control port and a base region of the thyristor can substantially modulate the potential of the base region. Another important consideration for thin capacitively coupled thyristors involves temperature-related operating effects thereof, such as temperature-related effects upon current passing and blocking states. For instance, in order to maintain a current passing state, thin capacitively-coupled thyristors require that a minimum holding current (IH) pass through the thyristor. The minimum IH, however, is temperature dependent as a result of temperature-related fluctuation of bipolar gains of the thyristor. Specifically, the IH required to maintain a current passing state of a thin capacitively-coupled thyristor tends to increase as the temperature decreases. Increases in IH are undesirable due to a corresponding increase in standby power required to maintain the current passing state of the thyristor. As another example, the forward blocking voltage of a thyristor tends to decrease at higher temperature. Decrease in forward blocking voltage is undesirable as it degrades the ability of the thyristor to maintain the current blocking state at higher temperatures.
These and other considerations have presented challenges to the implementation of such a thin capacitively-coupled thyristor, and in particular with applications susceptible to temperature fluctuations.